RTL Design Engineer

Working on complex Digital Subsystems for next-generation Satellite communication ASICs.

ASIC Design Verification.

Experience with SOC, Sub-System, or Block level verification.

Strong System Verilog/UVM testbench experience.

Drive Functional Coverage, Regressions, and verification signoff.

Experience working on DSP Systems is a plus.

Experience working on high-speed interfaces is a plus.

Remote-12 Months- up to 105/hr- No restriction on work authorization

• Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic.
• Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems.

Minimum Qualifications:

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field.
• 8+ years of post-college experience in digital design with proficiency in Verilog and System Verilog.
• Experience in RTL design for high-speed data paths or packet processing in ASICs.
• Deep understanding of Host Ethernet adaptor architectures.

Pay: $65.00 - $70.00 per hour

Expected hours: 8.0 per week

Work Location: Remote